May 2026 · IEEE OJ-COMS
Resilient and Interpretable Power Fingerprinting for IoT DDoS Defense
Published a privacy-centric, noise-resilient framework that detects attacks from physical-layer power signals and explains its decisions.
Edge AI & IoT Security
Building trustworthy intelligence for the edge.
Research Profile
I am a Ph.D. student at the Institute of Science Tokyo, supervised by Prof. Yuko Hara. My work combines hardware/software co-design, efficient machine learning, and security to build real-time intrusion detection systems for constrained IoT and edge platforms.
Interests
- FPGA
- Efficient Machine Learning
- Embedded Systems
- Internet of Things
- Intrusion Detection Systems
- Computer Architecture
Education
PhD in Information and Communications Engineering, 2023.10 ~ 2026.09
Institute of Science Tokyo (formerly Tokyo Institute of Technology)
MEng in Information and Communications Engineering, 2021.10 ~ 2023.09
Tokyo Institute of Technology
BEng in VLSI Design & System Integration, 2017.09 ~ 2021.06
Nanjing University
Research Areas
A hardware-aware approach to practical and trustworthy edge intelligence.
Efficient Edge AI
FPGA-based inference and feature selection for deterministic, low-latency detection.
Trustworthy Machine Learning
Interpretable, resilient models designed for constrained and imbalanced operating environments.
IoT Security
Network, provenance, and power side-channel defenses that preserve payload privacy.
Latest Updates
Recent research milestones and publications.
May 2026 · IEEE ICC
LiReS IDS for the RISC-V edge
Accepted work on a lightweight, real-time, and secure intrusion detection system for resource-constrained edge platforms.
September 2025 · ESORICS Workshop
Semantic-aware provenance-based intrusion detection
Presented a lightweight method that prioritizes security-critical events using semantic roles in provenance graphs.
Selected Publications
Recent work spanning hardware-assisted security, edge AI, and trustworthy intrusion detection.
Browse the complete publication archive for abstracts, citations, and available resources.
(2026).
LiReS IDS: A Lightweight, Real-time, and Secure Intrusion Detection System for RISC-V Edge.
IEEE International Conference on Communications (ICC), Glasgow, Scotland, May 2026. Accepted..
(2026).
Resilient and Interpretable Power Fingerprinting for IoT DDoS Defense.
IEEE Open Journal of the Communications Society, vol.7, pp.4574-4589, 2026.
(2025).
Semantic-Aware Provenance-Based Intrusion Detection for Edge Systems.
Workshop on Hardware-Supported Software Security in conjunction with ESORICS, pp. 397-406, Toulouse, France, Sept. 2025.
(2025).
Poster: Lightweight Network Intrusion Detection System for RISC-V Based Edge Devices.
IEEE European Symposium on Security and Privacy (EuroS&P), Venice, Italy, Jun. 2025.
(2025).
Lightweight Real-Time Detection of DDoS Attacks on IoT Devices via Power Side-Channel Analysis.
IEEE International Conference on Communications (ICC), pp. 1851-1856, Montreal, Canada, Jun. 2025.
(2025).
Hardware-Assisted IoT Security: Real-Time DDoS Detection through Power Side-Channel Analysis.
IEICE Tech. Rep., vol. 124, no. 400, VLD2024 103-140, pp. 194-199, Feb. 2025.
Professional Experience
Visiting Researcher
Université libre de Bruxelles
Hosted by the ULB Cybersecurity Research Center, I researched intrusion detection systems from dataset development to edge implementation.
Research Assistant
Institute of Science Tokyo
I contribute to Trustworthy Architecture, Cryptography, and Evaluation for IoT systems and Green-niX, with a focus on efficient and secure edge computing.
Research Intern
Polytechnique Montreal
I worked as a short-term researcher. The project codes and documents are available through the following link: https://github.com/qyz-pi/Scalable-Low-Complexity-Implementation-of-Constant-Matrix-Multiplication-Circuits/. My major research content included:
- Matrix multiplication optimization study
- Algorithm prototype implementation
- Hardware design with Verilog
Recognition
2023 SLDM Work-in-progress (WIP) Best Presentation Award
See certificateContact
- qyzeng [at] cad.ict.e.titech.ac.jp
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